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FEATURES High Slew Rate - 170 V/ s Wide Bandwidth - 28 MHz Fast Settling Time - <200 ns to 0.01% Low Offset Voltage - <500 V Unity-Gain Stable Low Voltage Operation 5 V to 15 V Low Supply Current - <10 mA Drives Capacitive Loads APPLICATIONS High Speed Image Display Drivers High Frequency Active Filters Fast Instrumentation Amplifiers High Speed Detectors Integrators Photo Diode Preamps GENERAL DESCRIPTION
Quad Precision, High Speed Operational Amplifier OP467
PIN CONNECTIONS 14-Lead Ceramic DIP (Y Suffix) and 14-Lead Plastic DIP (P Suffix)
OUT A 1 -IN A 2
+ +
14 OUT D 13 -IN D 12 +IN D
+IN A 3 V+ 4 +IN B 5 -IN B 6 OUT B 7
+ +
OP467
11 V- 10 +IN C 9 8 -IN C OUT C
16-Lead SOIC (S Suffix)
OUT A 1 -IN A +IN A V+ +IN B -IN B OUT B NC 2 3 4 5 6 7 8 16 OUT D 15 -IN D 14 +IN D
20-Terminal LCC (RC Suffix)
OUT A OUT D -IN A NC -IN D
The OP467 is a quad, high speed, precision operational amplifier. It offers the performance of a high speed op amp combined with the advantages of a precision operational amplifier all in a single package. The OP467 is an ideal choice for applications where, traditionally, more than one op amp was used to achieve this level of speed and precision. The OP467's internal compensation ensures stable unity-gain operation, and it can drive large capacitive loads without oscillation. With a gain bandwidth product of 28 MHz driving a 30 pF load, output slew rate in excess of 170 V/s, and settling time to 0.01% in less than 200 ns, the OP467 provides excellent dynamic accuracy in high speed data-acquisition systems. The channel-to-channel separation is typically 60 dB at 10 MHz. The dc performance of OP467 includes less than 0.5 mV of offset, voltage noise density below 6 nV/Hz, and total supply current under 10 mA. Common-mode rejection and power supply rejection ratios are typically 85 dB. PSRR is maintained to better than 40 dB with input frequencies as high as 1 MHz. The low offset and drift plus high speed and low noise make the OP467 usable in applications such as high speed detectors and instrumentation. The OP467 is specified for operation from 5 V to 15 V over the extended industrial temperature range (-40C to +85C) and is available in 14-lead plastic and ceramic DIP, and 16-lead SOIC and 20-terminal LCC surface-mount packages. Contact your local sales office for MIL-STD-883 data sheet and availability.
3 +IN A 4 NC 5 V+ 6 NC 7 +IN B 8 9
-IN B
2
1
20 19 18 +IN D 17 NC
OP467
13 V- 12 +IN C 11 -IN C 10 OUT C 9 NC
OP467
(TOP VIEW)
16 V- 15 NC 14 +IN C
10 11 12 13
OUT B OUT C -IN C NC
NC = NO CONNECT
NC = NO CONNECT
V+
+IN -IN
OUT
V-
Figure 1. Simplified Schematic
REV. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2004 Analog Devices, Inc. All rights reserved.
OP467-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Common-Mode Rejection Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Long-Term Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing POWER SUPPLY2 Power Supply Rejection Ratio Supply Current Supply Voltage Range DYNAMIC PERFORMANCE Gain Bandwidth Product Slew Rate Symbol VOS IB IOS CMR CMR AVO VOS/T IB/T VOS/T VO
(@ VS =
15.0 V, TA = 25 C unless otherwise noted.)
Min Typ 0.2 Max 0.5 1 600 700 100 150 Unit mV mV nA nA nA nA dB dB dB dB V/C pA/C V V V dB dB mA mA V MHz V/s V/s MHz ns Degrees pF pF V p-p nV/Hz pA/Hz
Conditions
-40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 12 V VCM = 12 V, -40C TA +85C RL = 2 k RL = 2 k, -40C TA +85C Note 1 RL = 2 k RL = 2 k, -40C TA +85C 4.5 V VS = 18 V -40C TA +85C VO = 0 V VO = 0 V, -40C TA +85C
80 80 83 77.5
150 150 10 10 90 88 86 3.5 0.2
750 13.0 12.9 96 86 4.5 28 125 170 350 2.7 200 45 2.0 1.0 13.5 13.12 120 115 8
PSRR ISY VS GBP SR
10 13 18
Full-Power Bandwidth Settling Time Phase Margin Input Capacitance Common Mode Differential NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
BW tS 0
AV = +1, CL = 30 pF VIN = 10 V Step, RL = 2 k, CL = 30 pF AV = +1 AV = -1 VIN = 10 V Step To 0.01%, VIN = 10 V Step
eN p-p eN iN
f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
0.15 6 8
NOTES 1 Long-Term Offset Voltage Drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at 125 C, with an LTPD of 1.3. 2 For proper operation the positive supply must be sequenced ON before the negative supply. Specifications subject to change without notice.
-2-
REV. E
OP467 ELECTRICAL CHARACTERISTICS (@ V =
S
5.0 V, TA = 25 C unless otherwise noted.)
Min Typ 0.3 Max 0.5 1 600 700 100 150 Unit mV mV nA nA nA nA dB dB dB dB V/C pA/C V V dB dB mA mA MHz V/s V/s MHz ns Degrees V p-p nV/Hz pA/Hz
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Common-Mode Rejection Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing POWER SUPPLY Power Supply Rejection Ratio Supply Current DYNAMIC PERFORMANCE Gain Bandwidth Product Slew Rate
Symbol VOS IB IOS CMR CMR AVO VOS/T IB/T VO
Conditions
-40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 2.0 V VCM = 2.0 V, -40C TA +85C RL = 2 k RL = 2 k, -40C TA +85C
125 150 20 76 76 80 74 85 80 83 35 0.2
RL = 2 k RL = 2 k, -40C TA +85C 4.5 V VS = 5.5 V -40C TA +85C VO = 0 V VO = 0 V, -40C TA +85C AV = +1 VIN = 5 V Step, RL = 2 k, CL = 39 pF AV = +1 AV = -1 VIN = 5 V Step To 0.01%, VIN = 5 V Step
3.0 3.0 92 83
3.5 3.20 107 105 8
PSRR ISY
10 12
GBP SR
22 90 90 2.5 280 45 0.15 7 8
Full-Power Bandwidth Settling Time Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
Specifications subject to change without notice.
BW tS 0 eN p-p eN iN
f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
REV. E
-3-
OP467 WAFER TEST LIMITS1 (@ V =
S
15.0 V, TA = 25 C unless otherwise noted.)
Symbol VOS IB IOS CMRR PSRR AVO VO ISY Conditions VCM = 0 V VCM = 0 V VCM = 12 V V = 4.5 V to 18 V RL = 2 k RL = 2 k VO = 0 V, RL = Limit 0.5 600 100 12 80 96 83 13.0 10 Unit mV max nA max nA max V min/max dB min dB min dB min V min mA max
Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range2 Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range Supply Current
NOTES 1 Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 2 Guaranteed by CMR test.
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Temperature Ranges Package Descriptions Package Options RC-Suffix (E-20A) Y-Suffix (Q-14) P-Suffix (N-14) S-Suffix (RW-16) S-Suffix (RW-16)
Supply Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . 26 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . Limited Storage Temperature Range Y, RC Packages . . . . . . . . . . . . . . . . . . . . -65C to +175C P, S Packages . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature Range OP467A . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C OP467G . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature Range Y, RC Packages . . . . . . . . . . . . . . . . . . . . -65C to +175C P, S Packages . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300C Package Type 14-Lead Cerdip (Y) 14-Lead PDIP (P) 16-Lead SOIC (S) 20-Terminal LCC (RC)
4 A JC
Model OP467ARC/883C OP467AY/883C OP467GBC OP467GP OP467GS OP467GS-REEL
-55C to +125C 20-Terminal LCC -55C to +125C 14-Lead Cerdip DIE -40C to +85C 14-Lead PDIP -40C to +85C 16-Lead SOIC -40C to +85C 16-Lead SOIC
DICE CHARACTERISTICS
Unit C/W C/W C/W C/W
94 76 88 78
10 33 23 33
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For proper operation the positive supply must be sequenced ON before the negative supply. 3 For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage. 4 JA is specified for the worst-case conditions, i.e., JA is specified for device in socket for cerdip, P-DIP, and LCC packages; JA is specified for device soldered in circuit board for SOIC package.
OP467 Die Size 0.111 0.100 inch, 11,100 sq. mils Substrate is Connected to V+, Number of Transistors 165
-4-
REV. E
Typical Performance Characteristics- OP467
80 70 60 GAIN
OPEN-LOOP GAIN - dB
100
VS = 15V RL = 1M CL = 30pF
PHASE SHIFT - Degrees
VS = 15V TA = 25 C 80
50 40 30 PHASE 20 10 0 -10 -20 1k 10k 100k 1M 10M 100M -90 -135 -180
IMPEDANCE -
60 AVCL = +100 40 AVCL = +10 20 AVCL = +1 0 100 1k 10k FREQUENCY - Hz 100k 1M
FREQUENCY - Hz
TPC 1. Open-Loop Gain, Phase vs. Frequency
TPC 4. Closed-Loop Output Impedance vs. Frequency
80 VS = 15V TA = 25 C 60
CLOSED-LOOP GAIN - dB
GAIN ERROR - dB
0.3 0.2 VS = 0.1 0.0 -0.1 -0.2 VS = 15V 5V
40
20
0
-0.3
-20 10k
100k
1M FREQUENCY - Hz
10M
100M
100k
1M FREQUENCY - Hz
3.4
5.8
10M
TPC 2. Closed-Loop Gain vs. Frequency
TPC 5. Gain Linearity vs. Frequency
25
30 AVCL = -1
MAXIMUM OUTPUT SWING - Volts
25 AVCL = +1 20
20
OPEN-LOOP GAIN - V/mV
15 TA = +125 C TA = +25 C 10 TA = -55 C 5
15
10 VS = 15V TA = 25 C RL = 2k
5
0 0 5 10 SUPPLY VOLTAGE - Volts 15 20
0 1k
10k
100k FREQUENCY - Hz
1M
10M
TPC 3. Open-Loop Gain vs. Supply Voltage
TPC 6. Max VOUT Swing vs. Frequency
REV. E
-5-
OP467
12 VS = 5V TA = 25 C
60 VS = 15V RL = 2k 50 VIN = 100mV p-p AVCL = -1 OVERSHOOT - % 40 AVCL = +1
MAXIMUM OUTPUT SWING - Volts
10
RL = 2k AVCL = +1
8 AVCL = -1 6
30
4
20
2
10
0 1k
0
10k
100k FREQUENCY - Hz
1M
10M
0
200
400
600 800 1000 1200 LOAD CAPACITANCE - pF
1400
1600
TPC 7. Max VOUT Swing vs. Frequency
TPC 10. Small Signal Overshoot vs. Load Capacitance
120 VS = 15V TA = 25 C 100
60 VS = 5V RL = 2k VIN = 100mV p-p AVCL = +1 AVCL = -1
COMMON-MODE REJECTION - Volts
50
80
OVERSHOOT - %
40
60
30
40
20
20
10
0 1k
0
10k
100k FREQUENCY - Hz
1M
10M
0
200
400
600 800 1000 1200 LOAD CAPACITANCE - pF
1400
1600
TPC 8. Common-Mode Rejection vs. Frequency
TPC 11. Small Signal Overshoot vs. Load Capacitance
120 VS = 15V TA = 25 C
60 VS = 50 40 15V
POWER SUPPLY REJECTION - dB
100
30
80
GAIN - dB
20 10 0 -10 -20 -30 CIN = NETWORK ANALYZER
1000pF 10000pF
500pF 200pF
60
40
20
0 100
1k
10k FREQUENCY - Hz
100k
1M
-40 10k
100k
1M FREQUENCY - Hz
10M
100M
TPC 9. Power-Supply Rejection vs. Frequency
TPC 12. Noninverting Gain vs. Capacitive Loads
-6-
REV. E
OP467
0 VS = -10 15V
4 3 2
VOUT ERROR - mV
CHANNEL SEPARATION - dB
-20 -30 -40 -50 -60 -70 -80 -90 -100 100 1k 10k 100k 1M FREQUENCY - Hz 10M 100M
VS = 15V VIN = 5V CL = 50pF
1 0 -1 -2 -3 -4 0 100 200 300 TIME - ns 400 500
TPC 13. Channel Separation vs. Frequency
TPC 16. Settling Time, Negative Edge
12
INPUT CURRENT NOISE DENSITY - pA/ Hz
4 5V < VS < 15V 3 2 VS = 15V VIN = 5V CL = 50pF
10
8
VOUT ERROR - mV
1 0 -1 -2
6
4
2 -3 0 1 10 100 FREQUENCY - Hz 1k -4 0 100 200 300 TIME - ns 400 500
TPC 14. Input Current Noise Density vs. Frequency
TPC 17. Settling Time, Positive Edge
100
20 TA = 25 C 15
INPUT VOLTAGE RANGE - Volts
10 5 0 -5 -10 -15
nV/ Hz
10
1.0 0.1
-20
1 10 100 FREQUENCY - Hz 1k 10k
0
5
10 SUPPLY VOLTAGE - Volts
15
20
TPC 15. Voltage Noise Density vs. Frequency
TPC 18. Input Voltage Range vs. Supply Voltage
REV. E
-7-
OP467
50 40 30 20
GAIN - dB
500
VS1 = 15V VS2 = 5V RL = 10k CL = 50pF
VS = 15V TA = 25 C 1252 OP AMPS 400
0 -10 VS2 = -20 -30 -40 -50 10k VS1 = 5V 15V
UNITS
200 100 0 -100
10
300
100k
1M FREQUENCY - Hz
10M
100M
-50
0
50
100
150
200
250
300
350
400
INPUT OFFSET VOLTAGE - VOS V
TPC 19. Noninverting Gain vs. Supply Voltage
TPC 22. Input Offset Voltage Distribution
14 VS = 15V TA = 25 C 12
500 VS = 5V TA = 25 C 1252 OP AMPS 400
OUTPUT SWING - Volts
10 POSITIVE SWING NEGATIVE SWING 6 UNITS 200 100 2 0 10 100 1k LOAD RESISTANCE - 10k 0 -100 8 300
4
-50
0
50
100
150
200
250
300
350
400
INPUT OFFSET VOLTAGE - VOS V
TPC 20. Output Swing vs. Load Resistance
TPC 23. Input Offset Voltage Distribution
5 VS = 5V TA = 25 C 4
500 VS = 15V TA = 25 C 1252 OP AMPS 400
POSITIVE SWING
OUTPUT SWING - Volts
3 NEGATIVE SWING 2
300 UNITS 200 100 0
10 100 1k LOAD RESISTANCE - 10k
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TC VOS - V/ C
TPC 21. Output Swing vs. Load Resistance
TPC 24. TC VOS Distribution
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REV. E
OP467
500 VS = 5V TA = 25 C 1252 OP AMPS 400
400 350 300
SLEW RATE - V/ s
VS = 5V RL = 2k AVCL = +1
300 UNITS
250 200 150 100
200
+SR -SR
100
50
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TC VOS - V/ C
0 -75
-50
-25
0 25 50 TEMPERATURE - C
75
100
125
TPC 25. TC VOS Distribution
TPC 28. Slew Rate vs. Temperature
60
29.0
650 GAIN BANDWIDTH PRODUCT - MHz 600 550 VS = 15V RL = 2k AVCL = -1
GBW
PHASE MARGIN - Degrees
55
VS = 15V RL = 2k
-SR
28.5
SLEW RATE - V/ s
500 450 400 350 300 +SR
50 M 45
28.0
27.5
40 -75
-50
-25
0
25
50
75
100
27.0 125
250 -75
-50
-25
TEMPERATURE - C
0 25 50 TEMPERATURE - C
75
100
125
TPC 26. Phase Margin and Gain Bandwidth vs. Temperature
TPC 29. Slew Rate vs. Temperature
400 350 300 VS = 5V RL = 2k AVCL = -1
SLEW RATE - V/ s
400 350 300 +SR 250 200 150 100 50 0 -75 VS = 15V RL = 2k AVCL = +1
SLEW RATE - V/ s
250 200
-SR
-SR
+SR 150 100 50 0 -75
-50
-25
0 25 50 TEMPERATURE - C
75
100
125
-50
-25
0 25 50 TEMPERATURE - C
75
100
125
TPC 27. Slew Rate vs. Temperature
TPC 30. Slew Rate vs. Temperature
REV. E
-9-
OP467
10
15V SUPPLY - Volts
4 2 0
0.1%
2 1 0 -5 -4
INPUT BIAS CURRENT - nA
6
0.01% 3
5V SUPPLY - Volts
8
RF = 5k TA = 25 C
5 4
200 VS = 160 15V
120
OUTPUT STEP FOR
OUTPUT STEP FOR
-2 -4 -6 -8 -10 0 100 200 SETTLING TIME - ns 300 0.1% 0.01%
80
-3 -2 -1 400
40
0 -75
-50
-25
0 25 50 TEMPERATURE - C
75
100
125
TPC 31. Settling Time vs. Output Step
TPC 33. Input Bias Current vs. Temperature
10
25 VS = INPUT OFFSET CURRENT - nA 15V
8
TA = +125 C TA = +25 C
20
SUPPLY CURRENT - mA
6
TA = -55 C
15
4
10
2
5
0 0
5
10 SUPPLY VOLTAGE - Volts
15
20
0 -75
-50
-25
0
25
50
75
100
125
TEMPERATURE - C
TPC 32. Supply Current vs. Supply Voltage
TPC 34. Input Offset Current vs. Temperature
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REV. E
OP467
APPLICATIONS INFORMATION Output Short-Circuit Performance
To achieve a wide bandwidth and high slew rate, the OP467 output is not short-circuit protected. Shorting the output to ground or to the supplies may destroy the device. For safe operation, the output load current should be limited so that the junction temperature does not exceed the absolute maximum junction temperature. To calculate the maximum internal power dissipation, the following formula can be used:
PD =
TJ
max- T A
effective. On the other hand, ceramic chip capacitors have excellent ESR and ESL (effective series inductance) performance at higher frequencies, and because of their small size, they can be placed very close to the device pin, further reducing the stray inductance. Best results are achieved by using a combination of these two capacitors. A 5 F-10 F tantalum parallel with a 0.1 F ceramic chip cap is recommended. If additional isolation from high frequency resonances of the power supply is needed, a ferrite bead should be placed in series with the supply lines between the bypass caps and the power supply. A word of caution: addition of the ferrite bead will introduce a new pole and zero to frequency response of the circuit and could cause unstable operation if it is not selected properly.
+VS + 10 F TANTALUM 0.1 F CERAMIC CHIP
JA
where TJ and TA are junction and ambient temperatures, respectively, PD is device internal power dissipation, and JA is packaged device thermal resistance given in the data sheet.
Unused Amplifiers
It is recommended that any unused amplifiers in a quad package be connected as a unity-gain follower with a 1 k feedback resistor with noninverting input tied to the ground plain.
Printed Circuit Board Layout Considerations
0.1 F CERAMIC CHIP - -VS 10 F TANTALUM
Satisfactory performance of a high speed op amp largely depends on a good PC layout. To achieve the best dynamic performance, following high frequency layout technique is recommended.
Grounding
Figure 2. Recommended Power Supply Bypass
Signal Considerations
A good ground plain is essential to achieve the optimum performance in high speed applications. It can significantly reduce the undesirable effects of ground loops and IR drops by providing a low impedance reference point. Best results are obtained with a multilayer board design with one layer assigned to ground plain. To maintain a continuous and low impedance ground, avoid running any traces on this layer.
Power Supply Considerations
Input and output traces need special attention to assure a minimum stray capacitance. Input nodes are very sensitive to capacitive reactance, particularly when connected to a high impedance circuit. Stray capacitance can inject undesirable signals from a noisy line into a high impedance input. Protect high impedance input traces by providing guard traces around them. This will also improve the channel separation significantly. Additionally, any stray capacitance in parallel with the op amp's input capacitance generates a pole in the frequency response of the circuit. The additional phase shift caused by this pole will reduce the circuit's gain margin. If this pole is within the gain range of the op amp, it will cause unstable performance. To reduce these undesirable effects, use the lowest impedance where possible. Lowering the impedance at this node places the poles at a higher frequency, far above the gain range of the amplifier. Stray capacitance on the PC board can be reduced by making the traces narrow and as short as possible. Further reduction can be realized by choosing smaller pad size, increasing the spacing between the traces, and using PC board material with a low dielectric constant insulator (dielectric constant of some common insulators: air = 1, Teflon(R) = 2.2, and FR4 = 4.7; with air being an ideal insulator). Removing segments of the ground plain directly under the input and output pads is recommended. Outputs of high speed amplifiers are very sensitive to capacitive loads. A capacitive load will introduce a pair of pole and zero to the circuit's frequency response, reducing the phase margin, leading to unstable operation or oscillation.
For proper operation the positive supply must be sequenced ON before the negative supply. All users should take steps to ensure this. In high frequency circuits, device lead length introduces an inductance in series with the circuit. This inductance, combined with stray capacitance, forms a high frequency resonance circuit. Poles generated by these circuits will cause gain peaking and additional phase shift, reducing the op amp's phase margin and leading to an unstable operation. A practical solution to this problem is to reduce the resonance frequency low enough to take advantage of the amplifier's power supply rejection. This is easily done by placing capacitors across the supply line and the ground plain as close as possible to the device pin. Since capacitors also have internal parasitic components, such as stray inductance, selecting the right capacitor is important. To be effective, they should have low impedance over the frequency range of interest. Tantalum capacitors are an excellent choice for their high capacitance/size ratio, but their ESR (effective series resistance) increases with frequency making them less
REV. E
-11-
OP467
Generally, it is good design practice to isolate the amplifier's output from any capacitive load by placing a resistor between the amplifier's output and the rest of the circuits. A series resistor of 10 to 100 is normally sufficient to isolate the output from a capacitive load. The OP467 is internally compensated to provide stable operation, and is capable of driving large capacitive loads without oscillation. Sockets are not recommended since they increase the lead inductance/capacitance and reduce the power dissipation of the package by increasing the leads' thermal resistance. If sockets must be used, use Teflon or pin sockets with the shortest possible leads.
Phase Reversal
DLY 4.806 s
100 90
10 0%
5V
5V
20ns
Figure 5. Saturation Recovery Time, Negative Rail
High Speed Instrumentation Amplifier
The OP467 is immune to phase reversal; its inputs can exceed the supply rails by a diode drop without any phase reversal.
V1
100
The OP467 performance lends itself to a variety of high speed applications, including high speed precision instrumentation amplifiers. Figure 6 represents a circuit commonly used for data acquisition, CCD imaging, and other high speed applications. Circuit gain is set by RG. A 2 k resistor will set the circuit gain to 2; for unity gain, remove RG. For any other gain settings use the following formula: G = 2/RG Resistor Value is in k RC is used for adjusting the dc common-mode rejection, and CC is used for ac common-mode rejection adjustments.
15.8V
OUTPUT
90
10
INPUT
0%
10V
10V
200 s
-VIN
CC
Figure 3. No Phase Reversal (AV = +1)
Saturation Recovery Time
2k 1k RG 1k 1.9k 10k +VIN 5pF RC 200 10T 10k 2k 2k OUTPUT
The OP467 has a fast and symmetrical recovery time from either rail. This feature is very useful in applications such as high speed instrumentation and measurement circuits, where the amplifier is frequently exposed to large signals that overload the amplifier.
DLY 9.842 s
100 90
Figure 6. A High Speed Instrumentation Amplifier
0.01% 10V STEP VS = 15V NEG SLOPE
10 0%
5V
5V
20ns
2.5mV -2.5mV
Figure 4. Saturation Recovery Time, Positive Rail
Figure 7. Instrumentation Amplifier Settling Time to 0.01% for a 10 V Step Input (Negative Slope)
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REV. E
OP467
0.01% 10V STEP VS = 15V POS SLOPE
2 MHz Biquad Bandpass Filter
2.5mV -2.5mV
The circuit in Figure 10 is commonly used in medical imaging ultrasound receivers. The 30 MHz bandwidth is sufficient to accurately produce the 2 MHz center frequency, as the measured response shows in Figure 11. When the op amp's bandwidth is too close to the filter's center frequency, the amplifier's internal phase shift causes excess phase shift at 2 MHz, which alters the filter's response. In fact, if the chosen op amp has a bandwidth close to 2 MHz, the combined phase shift of the three op amps will cause the loop to oscillate. Careful consideration must be given to the layout of this circuit as with any other high speed circuit.
Figure 8. Instrumentation Amplifier Settling Time to 0.01% for a 10 V Step Input (Positive Slope)
+VS + TO INPUT 2k +
If the phase shift introduced by the layout is large enough, it could alter the circuit performance, or worse, it will oscillate.
R6 1k C1 50pF
AD9617 1k
TO IN-AMP OUTPUT 2k - - -VS 549 61.9
ERROR TO SCOPE
2k
R2 2k R1 3k
R4 2k R3 2k
C2 50pF R5 2k
1/4 OP467 + 1/4 OP467 + -
-
1/4 OP467 + VOUT
-
-
1/4 OP467 +
VIN
Figure 9. Settling Time Measurement Circuit
Figure 10. 2 MHz Biquad Filter
0
-10
GAIN - dB
-20
-30
-40
10k
100k
1M FREQUENCY - Hz
10M
100M
Figure 11. Biquad Filter Response
REV. E
-13-
OP467
+5V +10V 1 2 C1 10pF VOUTA
1
VDD VREFA RFBA
DAC8408
DGND 28 VREFC 27 RFBC 26 IOUT 1C 25
+10V
3 4 5 6 7
C3 10pF
13
- OP467 +
+15V
2
IOUT 1A IOUT 2A/ IOUT 2B IOUT 1B RFBB VREFB DB0 (LSB) DB1
3
IOUT 2C/ 24 IOUT 2D IOUT 1D 23 RFBD 22
12
OP467 +
14
VOUTA
0.1 F
9
VOUTB
7
- OP467 11 +
4
6
8 C2 10pF +10V 9 10
VREFD
21 +10V DIGITAL CONTROL SIGNALS
DS2 20 DS1 19 R/W 18 A/B 17 (MSB) DB7 16 DB6 15
C4 10pF
10
OP467 +
8
VOUTB
5
0.1 F -15V 11 DB2 12 DB3 13 DB4 14 DB5
Figure 12. Quad DAC Unipolar Operation
Fast I-To-V Converter
The fast slew rate and fast settling time of the OP467 are well suited to the fast buffers and I-to-V converters used in a variety of applications. The circuit in Figure 12 is a unipolar quad DAC consisting of only two ICs. The current output of the DAC8408 is converted to a voltage by the OP467 configured as an I-to-V converter. This circuit is capable of settling to 0.1% within 200 ns. Figures 13 and 14 show the full-scale settling time of the outputs. To obtain reliable circuit performance, keep the traces from the DAC's IOUT to the inverting inputs of the OP467 short to minimize parasitic capacitance.
260.0ns
100 90
251.0ns
100 90
10 0%
2V
50mV
100ns
Figure 14. Voltage Output Settling Time
DAC-8408 RFB 3pF IOUT I-V OP467 2k 2k 1k AD847 604 60.4 50 DC OFFSET
10 0%
2V
50mV
100ns
Figure 13. Voltage Output Settling Time Figure 15. DAC VOUT Settling Time Circuit
-14-
REV. E
OP467
OP467 SPICE MACRO-MODEL
* Node assignments noninverting input inverting input positive supply negative supply output * . SUBCKT OP467 * * INPUT STAGE * I1 4 50 CIN 1 2 IOS 1 2 Q1 5 2 Q2 6 7 R3 99 5 R4 99 6 R5 8 4 R6 9 4 EOS 7 1 EREF 98 0 1 2 99 50 27
* * COMMON-MODE STAGE WITH ZERO AT 1.26 kHz * ECM 13 98 POLY (2) (1,20) (2,20) 0 0 . 5 0 . 5 R8 13 14 1E6 R9 14 98 25 . 119 C3 13 14 126 . 721E-12 * * POLE AT 400E6 * R10 15 98 C4 15 98 G2 98 15 * * OUTPUT STAGE * ISY 99 50 RMP1 99 20 RMP2 20 50 RO1 99 26 RO2 26 50 L1 26 27 GO1 26 99 GO2 50 26 G4 23 50 G5 24 50 V3 21 26 V4 26 22 D3 15 21 D4 22 15 D5 99 23 D6 99 24 D7 50 23 D8 50 24
10E-3 1E-12 5E-9 8 QN 9 QN 185 . 681 185 . 681 180 . 508 180 . 508 POLY (1) (14,20) 50E-6 (20,0) 1
1E6 0 . 398E-15 (10,20) 1E-6
1
* * GAIN STAGE AND DOMINANT POLE AT 1.5 kHz * R7 10 98 3 . 714E6 C2 10 98 28 . 571E-12 G1 98 10 (5,6) 5 . 386E-3 V1 99 11 1 . 6 V2 12 50 1 . 6 D1 10 11 DX D2 12 10 DX RC 10 28 1 . 4E3 CC 28 27 12E-12
-8 . 183E-3 96 . 429E3 96 . 429E3 200 200 1E-7 (99,15) 5E-3 (15,50) 5E-3 (15,26) 5E-3 (26,15) 5E-3 50 50 DX DX DX DX DY DY
* * MODELS USED * . MODEL QN NPN (BF=33.333E3) . MODEL DX D . MODEL DY D (BV=50) . ENDS OP467
99
99 RMP1 D5 D6 V3 +- 20 15 R10 G2 C4 98 RMP2 23 24 D7 D8 G5 G02 D4 22 V4 -+ D3 21 26 99
99 + - 11 D1 7 10 C3 13 R8 R9 + - ECM 98 12 + - V2 50 D2 14 RC 28 CC 27 V1
ISY
G01 R01
R3 5 2
L1 27
R4 6
15
N- IOS CIN 1 N+ 8 R5
Q1
Q2 9 4 R6
G1
R7
C2
R02
-+ - EOS I1 + EREF
+
- G4
EREF
50
50
50
Figure 16. SPICE Macro-Model Output Stage
Figure 17. SPICE Macro-Model Input and Gain Stage
REV. E
-15-
OP467
OUTLINE DIMENSIONS
14-Lead Plastic Dual In-Line Package [PDIP] (N-14) P-Suffix
Dimensions shown in inches and (millimeters)
14-Lead Ceramic Dual In-Line Package [CERDIP] (Q-14) Y-Suffix
Dimensions shown in inches and (millimeters)
0.685 (17.40) 0.665 (16.89) 0.645 (16.38)
14 1 8 7
0.005 (0.13) MIN
0.295 (7.49) 0.285 (7.24) 0.275 (6.99)
14
0.098 (2.49) MAX
8 7
PIN 1
1
0.310 (7.87) 0.220 (5.59) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38)
0.100 (2.54) BSC
0.100 (2.54) BSC 0.015 (0.38) MIN 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) SEATING PLANE
0.785 (19.94) MAX
0.325 (8.26) 0.310 (7.87) 0.300 (7.62)
0.200 (5.08) MAX
0.150 (3.81) 0.135 (3.43) 0.120 (3.05)
0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.150 (3.81) MIN 0.070 (1.78) SEATING 15 PLANE 0 0.030 (0.76)
0.015 (0.38) 0.008 (0.20)
0.022 (0.56) 0.060 (1.52) 0.018 (0.46) 0.050 (1.27) 0.014 (0.36) 0.045 (1.14)
0.015 (0.38) 0.010 (0.25) 0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
16-Lead Standard Small Outline Package [SOIC] Wide Body (RW-16) S-Suffix
Dimensions shown in millimeters and (inches)
20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20A) RC-Suffix
Dimensions shown in inches and (millimeters)
0.100 (2.54) 0.064 (1.63)
0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90)
19 18 20 1
10.50 (0.4134) 10.10 (0.3976)
3 4
0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC
16
9
0.358 (9.09) 0.342 (8.69) SQ
7.60 (0.2992) 7.40 (0.2913)
0.358 (9.09) MAX SQ
0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.055 (1.40) 0.045 (1.14)
BOTTOM VIEW
14 13 8 9
1
8
10.65 (0.4193) 10.00 (0.3937)
0.088 (2.24) 0.054 (1.37)
45 TYP 0.150 (3.81) BSC
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
45
COPLANARITY 0.10
SEATING PLANE
8 0.33 (0.0130) 0 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
-16-
REV. E
OP467 Revision History
Location 3/04--Data Sheet changed from REV. D to REV. E. Page
Changes to TPC 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4/01--Data Sheet changed from REV. C to REV. D.
Footnote added to POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Footnote added to MAX RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to POWER SUPPLY CONSIDERATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
REV. E
-17-
-18-
-19-
-20-
C00302-0-3/04(E)
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